With increasing levels of integration in semiconductor chips or dies, such as those with a silicon substrate, several conflicting demands are put on the integrated circuit process. Today's circuits demand high performance and high density, but also require low leakage currents to minimize power consumption. As the layout of the integrated circuit positions the transistors closer and closer together, it becomes increasing difficult to isolate the transistors so that parasitic leakage currents do not result.
Isolation of the transistors is generally accomplished by separating the individual transistors areas with a insulating material such as an oxide of silicon. The isolation, commonly known as field oxidation, is formed by a method known as LOCOS in which the transistor area is masked and the isolation area is thermally oxidized, or by a trench isolation method in which an opening is forming in the silicon and filled with insulation. Normally, the trench, which varies in width, is a shallow trench in depth and is known as shallow trench isolation or STI.
The field oxide is formed before the transistors with both of the LOCOS and STI methods. The STI provides the advantage of using less silicon than LOCOS thereby permitting a greater number of transistors for the same amount of silicon. However, STI is still susceptible to the formation of parasitic transistors under the field oxide or leakage along the edge of the field oxide.
One method to ensure that leakage does not occur along the edge of the STI isolation at the end of the transistor is to overlap the transistor's gate electrode onto the isolation areas. This overlap accommodates any gate-to-isolation misalignment and any gate pullback, both of which can occur during the forming of lithography pattern of the gate electrode. Although this overlap guarantees that the gate electrode does not leave a leakage path along the edge of the isolation, it unfortunately, limits how close two transistors can be positioned since the gate lithography process must be able to define the space between the gate ends of the two transistors.